1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a plurality of memory devices together with a plurality of high voltage devices and a plurality of low voltage devices.
2. Description of Related Art
Generally, on the same chip, some of the integrated circuits need both low voltage devices and high voltage devices. For example, the erasable programmable ROM (EPROM) needs high voltage transistors to perform the programming operations and the low voltage transistor for logic operations. Since the high voltage devices and the low voltage devices need different supply voltage, the thicknesses of the gate dielectric layers of the high voltage devices and the low voltage devices are different from each other. For the high voltage devices, the thickness of the gate dielectric layer should be large enough to sustain the relatively high applied voltage. On the other hand, for the low voltage devices, the thickness of the gate dielectric layer is relatively small. Furthermore, for the memory, the thickness of the tunnel dielectric layer is relatively small as well.
With the increasing of the demands for the smaller and smaller devices, the challenge for shrinking down the size of the memory is high. Conventionally, after the buried diffusion region for the memory is formed in the substrate, the high thermal budget of the later performed process, such as the formation of the relatively thick dielectric layer, seriously affects the size of the buried diffusion region. That is, the relatively high temperature leads to the extension of the buried diffusion region. Therefore, it is hard to control the device characteristics of the memory. Accordingly, how to well control the size of the buried diffusion region of the memory without being enlarged during the process procedure becomes a main task for the present technology development.